Instinct MI300X
AMDdatacenter| Overview | |
|---|---|
| Architecture | CDNA 3 (2023) |
| Launch date | 2023-12-06 |
| Process node | TSMC 5nm | 6nm FinFET |
| Transistor count | 153B |
| GPU target (gfx) | gfx942 |
| Memory | |
| VRAM | 192 GB HBM3 |
| Memory bandwidth | 5,325 GB/s |
| Cache | 256 MB |
| ECC | Yes |
| Compute — vector | |
| FP64 | 81.7 TFLOPS |
| FP32 | 163.4 TFLOPS |
| Compute — matrix / tensor | |
| FP64 | 163.4 TFLOPS |
| TF32 | 653.7 TFLOPS |
| BF16 | 1,307.4 TFLOPS |
| FP16 (dense / sparse) | 1,307.4 / 2,614.9 TFLOPS |
| FP8 (dense / sparse) | 2,614.9 / 5,229.8 TFLOPS |
| INT8 (dense / sparse) | 2,600 / 5,220 TOPS |
| Cores & clocks | |
| Compute Units | 304 |
| Shader cores | 19,456 |
| Matrix / Tensor cores | 1,216 |
| Peak clock | 2,100 MHz |
| Board & system | |
| TDP | 750 W |
| Form factor | OAM Module |
| Cooling | Passive OAM |
| PCIe | PCIe 5.0 x16 |
| Interconnect | Infinity Fabric — 128 GB/s |
| Multi-instance support | SR-IOV |
Compatible ROCm versions
Source: AMD's official product/spec page (amd.com/en/products/accelerators/instinct/mi300/mi300x.html, "Expand All" spec accordion), pulled 2026-09-01, cross-checked against this file's previously-recorded MI300X/MI325X datasheet decimal figures.
fp16TFLOPS/fp8TFLOPS and their Sparse variants keep the earlier brochure-precision figures (1,307.4 / 2,614.9 / 2,614.9 / 5,229.8) rather than the product page's rounded PFLOP figures (1.3/2.61/2.61/5.22 PFLOPs) — same underlying numbers, brochure carries one more significant digit. Unlike the CDNA4 (MI350-series) pages, MI300X's page publishes only ONE FP16 figure ("Peak Half Precision (FP16) Performance", no separate "Matrix" vs. vector split) — treated as the matrix/tensor rate here (fp16TFLOPSVector intentionally omitted, not zero) since 1.3 PFLOPs is far above FP32 vector throughput and can only be a tensor-core rate.
fp64TFLOPS (81.7, vector) and fp64TFLOPSMatrix (163.4) genuinely DIFFER on this part — unlike MI350X/MI355X where AMD lists identical vector/matrix FP64 figures, MI300X's matrix engines run FP64 at exactly 2x the vector rate. fp32TFLOPS uses the page's "FP32 Matrix" and plain "FP32" figures, which are identical (163.4) on this part.
tf32TFLOPS (653.7, dense) is new to this collection — MI300X/CDNA3 publishes a TF32 matrix rate (AMD's answer to NVIDIA's Tensor Float 32) that CDNA4 (MI350-series) no longer lists; its structured-sparsity variant (~1.3 PFLOPs, ~2x) isn't captured in a separate field. bf16TFLOPS is set equal to fp16TFLOPS: the page's "Peak bfloat16" figure (1.3 PFLOPs) matches FP16 exactly, same pattern as every other Instinct part in this collection. int8TOPS/int8TOPSSparse (2,600/5,220 POPs) are the page's own values at their native precision — no separate brochure decimal available.
tdpWatts (750) is labelled "Typical Board Power (TBP)" on the page but the value itself reads "750W Peak" — kept as-is, same figure this collection has always used for MI300X. interconnectBandwidthGBs (128) is the page's single "Peak Infinity Fabric Link Bandwidth" figure across 8 links; MI300X's page (unlike MI350-series) doesn't publish a separate scale-up/scale-out breakdown. No msrpUSD — AMD doesn't publish Instinct list prices; unofficial street-price estimates (~$15,000) are deliberately not used.