Instinct MI300A

AMDdatacenter
Overview
ArchitectureCDNA 3 (2023)
Process nodeTSMC 5nm | 6nm FinFET
GPU target (gfx)gfx942
Memory
VRAM128 GB HBM3 (unified CPU+GPU)
Memory bandwidth5,300 GB/s
Cache256 MB
ECCYes
Compute — vector
FP6461.3 TFLOPS
FP32122.6 TFLOPS
Compute — matrix / tensor
FP64122.6 TFLOPS
TF32490.3 TFLOPS
BF16980.6 TFLOPS
FP16 (dense / sparse)980.6 / 1,961.2 TFLOPS
FP8 (dense / sparse)1,961.2 / 3,922.4 TFLOPS
INT81,961 TOPS
Cores & clocks
Compute Units228
Shader cores14,592
Matrix / Tensor cores912
Peak clock2,100 MHz
Board & system
TDP550 W
Form factorSH5 socket (APU, not an OAM/PCIe card)

Compatible ROCm versions

6.0.06.0.26.1.06.1.16.1.26.1.56.2.06.2.16.2.26.2.46.3.06.3.16.3.26.3.36.4.06.4.16.4.26.4.37.0.07.0.17.0.27.1.07.1.17.2.07.2.17.2.27.2.37.2.47.14.010.0.0
Added 2026-09-06 during a `gpus` coverage pass -- an APU sibling of the already-tracked MI300X (same CDNA 3 die family, same gfx942 target) that integrates 24 Zen 4 x86 CPU cores alongside the GPU chiplets on one package, sharing one pool of HBM3 as unified CPU+GPU memory (hence 128GB here vs. MI300X's 192GB -- some HBM/die budget goes to the CPU side instead). This CPU core count isn't captured in any field of this GPU-focused schema; noted here since it's the entire point of this SKU and not otherwise visible on this page. AMD's own MI300A datasheet PDF timed out on direct fetch (same issue as MI210 above); figures instead come from secondary aggregators (gpucost.org, cputronic.com), cross-checked by linear-scaling from this site's already- verified MI300X entry using the 228/304 = 0.75 ratio of MI300A's to MI300X's compute-unit count (both run at the same 2100MHz peak clock): 0.75 x MI300X's fp32TFLOPS (163.4) = 122.55 -> matches the sourced 122.6 almost exactly; 0.75 x MI300X's fp64TFLOPS/fp64TFLOPSMatrix (81.7/163.4) = 61.275/122.55 -> matches 61.3/122.6; 0.75 x MI300X's tf32TFLOPS (653.7) = 490.275 -> matches 490.3. matrixCoreCount (912) and shaderCoreCount (14,592) both reduce to the exact same per-CU ratios MI300X's page confirms directly (4 matrix cores and 64 stream processors per CU). The secondary sources label several of these as "with sparsity" figures, but the numbers themselves match MI300X's DENSE figures scaled by 0.75, not its sparse figures (which would be roughly double) -- treated as a mislabeling in those sources rather than a real dense/sparse difference, so fp16TFLOPS/fp8TFLOPS above are recorded as dense, with fp16TFLOPSSparse/fp8TFLOPSSparse then derived by doubling, matching the dense:sparse ratio already established on the MI300X entry. int8TOPS (1,961) reuses the fp8TFLOPS dense figure -- no MI300A-specific INT8 number distinct from FP8 was found in any source consulted (MI300X's own page does publish a slightly different INT8 figure from its FP8 one, 2,600 vs. 2,614.9, so this may be an oversimplification, not a confirmed match). tdpWatts (550) is AMD's stated air/liquid-cooled maximum; a 760W figure also appears in the same sources for a liquid-cooled-only configuration, not used here to match this collection's convention elsewhere (MI250X) of using the lower/typical figure when two are published. No pcieGen, interconnectBandwidthGBs, multiInstanceSupport, transistorCountBillion, or msrpUSD -- none were found specifically confirmed for this SKU (as opposed to assumed identical to MI300X), so left unset rather than guessed.

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