Instinct MI250X
AMDdatacenter| Overview | |
|---|---|
| Architecture | CDNA 2 (2021) |
| Launch date | 2021-11-08 |
| Process node | TSMC 6nm FinFET |
| GPU target (gfx) | gfx90a |
| Memory | |
| VRAM | 128 GB HBM2e |
| Memory bandwidth | 3,276.8 GB/s |
| ECC | Yes |
| Compute — vector | |
| FP64 | 47.9 TFLOPS |
| FP32 | 47.9 TFLOPS |
| Compute — matrix / tensor | |
| FP64 | 95.7 TFLOPS |
| BF16 | 383 TFLOPS |
| FP16 | 383 TFLOPS |
| INT8 | 383 TOPS |
| INT4 | 383 TOPS |
| Cores & clocks | |
| Compute Units | 220 |
| Shader cores | 14,080 |
| Peak clock | 1,700 MHz |
| Board & system | |
| TDP | 500 W |
| Form factor | OAM Module |
| Cooling | Passive OAM |
| PCIe | PCIe 4.0 x16 |
| Interconnect | Infinity Fabric (3rd gen) — 100 GB/s |
| Multi-instance support | N/A |
Compatible ROCm versions
fp8TFLOPS omitted — CDNA 2 has no native FP8 matrix support (added in CDNA 3 with MI300). No "Matrix Cores" count or transistor count is published for this generation (AMD started listing those with MI300/CDNA3) — matrixCoreCount intentionally omitted rather than guessed. MI250X is a dual-die (OAM) module; the page lists TDP as "500W | 560W Peak" — 500W (typical) kept as tdpWatts, matching this file's prior figure. fp32TFLOPS uses the plain (non-matrix) "Peak Single Precision (FP32) Performance" figure (47.9) for consistency with how this collection reports vector FP32 elsewhere; the page's separate "FP32 Matrix" figure (95.7, 2x vector) is not captured in its own field for this older generation. fp64TFLOPS (47.9, vector) and fp64TFLOPSMatrix (95.7, 2x) do differ, matching the FP32 pattern. bfloat16 and FP16 are published as identical figures (383 TFLOPs), used for both bf16TFLOPS and fp16TFLOPS. multiInstanceSupport set to N/A — no SR-IOV/MIG-equivalent partitioning is listed on this page (introduced starting with MI300-series). Source: AMD's official product/spec page (amd.com/en/products/accelerators/instinct/mi200/mi250x.html, "Expand All" spec accordion), pulled 2026-09-01.