Instinct MI100
AMDdatacenter| Overview | |
|---|---|
| Architecture | CDNA 1 (2020) |
| Launch date | 2020-11-16 |
| Process node | TSMC 7nm FinFET |
| GPU target (gfx) | gfx908 |
| Memory | |
| VRAM | 32 GB HBM2 |
| Memory bandwidth | 1,200 GB/s |
| ECC | Yes |
| Compute — vector | |
| FP64 | 11.5 TFLOPS |
| FP32 | 23.1 TFLOPS |
| Compute — matrix / tensor | |
| BF16 | 92.3 TFLOPS |
| FP16 | 184.6 TFLOPS |
| INT8 | 92.3 TOPS |
| INT4 | 92.3 TOPS |
| Cores & clocks | |
| Compute Units | 120 |
| Shader cores | 7,680 |
| Peak clock | 1,502 MHz |
| Board & system | |
| TDP | 300 W |
| Form factor | PCIe Add-in Card |
| Cooling | Passive |
| PCIe | PCIe 4.0 x16, PCIe 3.0 x16 |
| Interconnect | Infinity Fabric — 92 GB/s |
| Multi-instance support | N/A |
Compatible ROCm versions
fp8TFLOPS omitted — CDNA 1 predates FP8 matrix support (added in CDNA 3 with MI300). No transistor count or Matrix Cores count is published for this generation. Unlike MI250X/MI300-series, bfloat16 (92.3 TFLOPs) is HALF of fp16TFLOPS (184.6) on this part rather than equal to it — AMD's page lists them as genuinely different rates here; int8TOPS/int4TOPS (92.3 each) match the bf16 rate, not the fp16 rate. No separate FP64/FP32 matrix figures are published — only the single "Peak Double/Single Precision (FP64/FP32) Performance" rows, used directly (FP32 Matrix and FP32 vector figures happen to be identical on this page, 23.1, so only one field is populated). No msrpUSD — AMD doesn't publish Instinct list prices. multiInstanceSupport set to N/A — no SR-IOV/partitioning listed (introduced starting with MI300-series). Source: AMD's official product/spec page (amd.com/en/products/accelerators/instinct/mi100.html, "Expand All" spec accordion), pulled 2026-09-01.