TITAN RTX

NVIDIAconsumer
Overview
ArchitectureTuring (2018)
Launch dateDec 2018
Compute capability7.5
Memory
VRAM24 GB GDDR6
Memory bandwidth672 GB/s
Compute — vector
FP3216.3 TFLOPS
Compute — matrix / tensor
FP16130 TFLOPS
Cores & clocks
Streaming Multiprocessors72
Shader cores4,608
Matrix / Tensor cores576
Peak clock1,770 MHz
Board & system
TDP280 W
PCIePCIe Gen3 x16
InterconnectNVLink (optional bridge) — 100 GB/s
MSRP$2,499

Compatible CUDA Toolkit versions

10.010.110.211.211.311.611.711.812.012.112.212.312.412.512.612.812.913.013.113.213.3
Added 2026-09 alongside GTX 1080 Ti, TITAN X (Pascal), and TITAN V — the last of NVIDIA's consumer/prosumer TITAN line (no successor was released after Ampere), and notable for pairing Turing's Tensor Cores with 24GB of VRAM, unusually large for a non-datacenter card at the time. CUDA core count (4,608), Tensor core count (576), boost clock (1,770 MHz), memory config (24GB GDDR6), memory bandwidth (672 GB/s), Tensor performance ("130 Tensor TFLOPs"), and the optional NVLink bridge (100 GB/s, doubling effective VRAM to 48GB across two cards) are all quoted directly from NVIDIA's own official product page (nvidia.com/en-us/titan/titan-rtx/), read 2026-09. fp32TFLOPS (16.3) and tdpWatts (280) aren't on that specific page but are consistently corroborated across independent GPU databases and contemporaneous press coverage of the Dec 2018 launch. int8TOPS is intentionally omitted, not guessed — secondary sources disagree sharply on this figure (some report 130 TOPS, equal to the FP16 Tensor rate; others report roughly double), and no NVIDIA-published number was found to resolve the conflict. msrpUSD (2499) is the original launch price, well-corroborated but not itself quoted on the current product page (it no longer lists a price). RT Core count/TFLOPS are published but out of scope for this AI/ML-focused schema, matching this collection's existing convention (see RTX 4090's notes for the same treatment). 2026-09-15 — added computeUnitCount (72 SMs). NVIDIA's TITAN RTX page gives 4,608 CUDA cores, 576 Tensor Cores and 72 RT Cores; on Turing's fixed per-SM structure all three independently give 72 SMs (4,608 / 64, 576 / 8, and one RT Core per SM). Recorded as a derived value rather than left blank because three published figures agree on it.

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