T4
NVIDIAdatacenter| Overview | |
|---|---|
| Architecture | Turing (2018) |
| Launch date | Sep 2018 (announced); product brief dated Dec 2018 |
| Compute capability | 7.5 |
| Memory | |
| VRAM | 16 GB GDDR6 |
| Memory bandwidth | 300 GB/s |
| ECC | Yes |
| Compute — vector | |
| FP32 | 8.1 TFLOPS |
| Compute — matrix / tensor | |
| FP16 | 65 TFLOPS |
| INT8 | 130 TOPS |
| INT4 | 260 TOPS |
| Cores & clocks | |
| Streaming Multiprocessors | 40 |
| Shader cores | 2,560 |
| Matrix / Tensor cores | 320 |
| Board & system | |
| TDP | 70 W |
| Form factor | Low-Profile PCIe |
| PCIe | PCIe Gen3 |
| Interconnect | PCIe only (no NVLink) — 32 GB/s |
Compatible CUDA Toolkit versions
Added 2026-09 alongside V100/P100/RTX 3090 — T4 is one of the most widely deployed inference GPUs in the field (cloud instances, edge inference) and was a notable gap in this site's NVIDIA coverage. All figures sourced directly from NVIDIA's official T4 datasheet (nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-t4/ t4-tensor-core-datasheet-951643.pdf, footer dated Mar19), read via pdftotext.
fp16TFLOPS (65) is the datasheet's "Mixed-Precision (FP16/FP32)" Tensor Core row — Turing's Tensor Cores (2nd gen) predate structured sparsity (introduced with Ampere), so there's no dense/sparse split and no fp16TFLOPSSparse value; likewise int8TOPS (130) and int4TOPS (260) are single dense figures with no sparse counterpart. No BF16, TF32, or FP8 Tensor rows exist for Turing (BF16/TF32 arrived with Ampere, FP8 with Hopper/Ada) — correctly omitted rather than left as zero. fp16TFLOPSVector is also omitted: the datasheet doesn't give a separate non-Tensor FP16 figure.
interconnect is PCIe-only — T4 has no NVLink, unlike the SXM-form-factor datacenter parts elsewhere in this collection; interconnectBandwidthGBs (32) is the x16 PCIe Gen3 host link bandwidth, explicitly labeled "Interconnect Bandwidth: 32 GB/sec" in the same table (separate from the "System Interface: x16 PCIe Gen3" row). tdpWatts (70) matches T4's signature low-profile single-slot design — no external power connector needed. No transistor count, process node, or MSRP in this datasheet — T4 shipped through OEM/server/cloud partners, not direct retail.
2026-09-15 — added computeUnitCount (40 SMs). NVIDIA's T4 datasheet publishes 2,560 CUDA cores and 320 Tensor Cores (both already recorded here) but no SM count; 40 follows independently from either one on Turing's fixed per-SM structure — 2,560 / 64 FP32 cores per SM = 40, and 320 / 8 Tensor Cores per SM = 40. Two agreeing ratios, so it is recorded as a value rather than left blank.