L40S

fp16TFLOPS/fp8TFLOPS dense figures and their Sparse counterparts are directly published dense/sparse pairs from NVIDIA's official L40S datasheet (362.05/733 dense; 733/1466 with structured sparsity) — original source verified in an earlier session. fp32TFLOPS (91.6) and tf32TFLOPS (183 dense, 366 with sparsity) added 2026-09-01 from NVIDIA's current L40S product page (nvidia.com/en-us/data-center/l40s/, "Specifications" panel) via screenshot (the page renders this panel in a way get_page_text and WebFetch on the linked datasheet PDF both failed to extract as text — read visually instead). bf16TFLOPS assumed equal to fp16TFLOPS (NVIDIA doesn't list BF16 separately on this page; Ada Lovelace Tensor Cores run BF16 and FP16 at the same rate on every other entry in this collection where both are independently published). No interconnect/interconnectBandwidthGBs — L40S has no NVLink, PCIe Gen4 x16 only. No transistor count or L2 cache found in text form (the page also shows an "RT Core Performance: 212 TFLOPS" ray-tracing figure, not included — out of scope for this AI/ML-focused schema). No public MSRP — L40S ships through the OEM/server-partner channel, not direct retail. 2026-09-15 — added shaderCoreCount (18,176 CUDA cores) and matrixCoreCount (568 fourth-generation Tensor Cores), both read from the specifications table on NVIDIA's own L40S product page (nvidia.com/en-us/data-center/l40s/) — they were on the page all along and simply missed on the earlier pass, not newly published. Also added computeUnitCount (142 SMs), which NVIDIA does not state directly but which both published counts independently imply on Ada Lovelace's fixed per-SM structure: 18,176 / 128 FP32 cores per SM = 142, and 568 / 4 Tensor Cores per SM = 142. The same table's "142 third-generation RT Cores" is a third confirmation, since Ada carries exactly one RT Core per SM. Three agreeing figures is why this is recorded as a value rather than left blank.