H100 SXM5 80GB
NVIDIAdatacenter| Overview | |
|---|---|
| Architecture | Hopper (2022) |
| Compute capability | 9.0 |
| Memory | |
| VRAM | 80 GB HBM3 |
| Memory bandwidth | 3,350 GB/s |
| Compute — vector | |
| FP64 | 34 TFLOPS |
| FP32 | 67 TFLOPS |
| Compute — matrix / tensor | |
| FP64 | 67 TFLOPS |
| TF32 | 494.5 TFLOPS |
| BF16 | 989.5 TFLOPS |
| FP16 (dense / sparse) | 989.5 / 1,979 TFLOPS |
| FP8 (dense / sparse) | 1,979 / 3,958 TFLOPS |
| INT8 (dense / sparse) | 1,979 / 3,958 TOPS |
| Cores & clocks | |
| Streaming Multiprocessors | 132 |
| Shader cores | 16,896 |
| Matrix / Tensor cores | 528 |
| Board & system | |
| TDP | 700 W |
| Form factor | SXM |
| PCIe | PCIe Gen5 |
| Interconnect | NVLink — 900 GB/s |
| Multi-instance support | Up to 7 MIGs @ 10GB each |
Compatible CUDA Toolkit versions
All figures sourced from NVIDIA's official H100 product page (nvidia.com/en-us/data-center/h100/, "Product Specifications" table, H100 SXM column), pulled 2026-09-01.
tf32TFLOPS, bf16TFLOPS, fp16TFLOPS, fp8TFLOPS, and int8TOPS are dense (non-sparse) figures, derived by halving NVIDIA's own published "with sparsity" headline numbers (989/1,979/1,979/3,958/3,958 respectively) — the page's own footnote ("* With sparsity") confirms this 2x convention, applied consistently across this site's Ampere/Hopper/Ada/Blackwell entries. The ...Sparse fields hold the vendor's directly published headline figures. fp64TFLOPS (34) and fp64TFLOPSMatrix (67) are NOT marked with the sparsity footnote in NVIDIA's table, so both are used as-is with no halving.
interconnectBandwidthGBs (900) is NVLink; the SXM module also exposes a PCIe Gen5 x16 host link at 128GB/s (pcieGen records the generation only). tdpWatts (700) is "Up to 700W (configurable)" per NVIDIA — the actual board default may run lower. No transistor count, L2 cache size, or process node published on this product page or in the quick-reference datasheet (the SM / CUDA-core / Tensor-core counts were missing for the same reason and have since been added from NVIDIA's Hopper architecture blog — see below). No msrpUSD — H100 ships through OEM/server partners, not direct retail.
2026-09-15 — added computeUnitCount (132 SMs), shaderCoreCount (16,896 FP32 CUDA cores) and matrixCoreCount (528 fourth-generation Tensor Cores) from NVIDIA's own "NVIDIA Hopper Architecture In-Depth" developer blog post (developer.nvidia.com/blog/nvidia-hopper-architecture-in-depth/), which gives the shipping H100 SXM5 configuration explicitly rather than the full GH100 die (144 SMs / 18,432 FP32 cores / 576 Tensor Cores — 12 SMs are fused off on every SXM5 part). None of these three figures appear on the H100 product page or in the quick-reference datasheet used for every other field here.