B300 (Blackwell Ultra)
NVIDIAdatacenter| Overview | |
|---|---|
| Architecture | Blackwell Ultra (2026) |
| Compute capability | 10.0 |
| Memory | |
| VRAM | 288 GB HBM3e |
| Memory bandwidth | 8,000 GB/s |
| Compute — vector | |
| FP64 | 1.25 TFLOPS |
| FP32 | 75 TFLOPS |
| Compute — matrix / tensor | |
| FP64 | 1.25 TFLOPS |
| TF32 | 1,125 TFLOPS |
| BF16 | 2,250 TFLOPS |
| FP16 (dense / sparse) | 2,250 / 4,500 TFLOPS |
| FP8 (dense / sparse) | 4,500 / 9,000 TFLOPS |
| FP6 (MXFP6) | 4,500 TFLOPS |
| FP4 (MXFP4 / NVFP4) | 13,500 TFLOPS |
| Cores & clocks | |
| Streaming Multiprocessors | 160 |
| Shader cores | 20,480 |
| Matrix / Tensor cores | 640 |
| Board & system | |
| TDP | 1400 W |
| Form factor | SXM |
| PCIe | PCIe Gen5 |
| Interconnect | NVLink — 1,800 GB/s |
Compatible CUDA Toolkit versions
Newly launched (NVIDIA's own DGX B300 page: "NVIDIA DGX B300 Systems Are Shipping Now") — added alongside AMD's MI350X/MI355X/MI455X as the current-generation refresh this collection was missing. B300's precise CUDA compute capability is sm_103 (distinct from B200's sm_100), but targetId here uses "10.0" to match this site's existing, already- documented convention of bucketing minor Blackwell steppings under the primary compute-capability value shown in the `cuda` collection (see cuda/12-8.yaml's notes) rather than introducing an unmatched "10.3" that would silently fail to cross-link to any CUDA entry.
Updated 2026-09-01: per-GPU compute figures now sourced from NVIDIA's HGX B300/HGX B200 comparison table (nvidia.com/en-us/data-center/hgx/, "HGX Specifications" section, HGX B300 column), which gives true 8-GPU totals per precision that this site derives to per-GPU by /8 — the standalone Blackwell Ultra PDF datasheet (linked from that page) is behind a lead-gen form (resources.nvidia.com) and wasn't accessible. fp4TFLOPS/fp6TFLOPS are new fields not previously captured; fp8TFLOPS/ fp16TFLOPS are unchanged from the prior derivation (confirmed independently against this new source — identical 4,500/2,250 dense values).
All values below are dense (non-sparse); NVIDIA's table states each row as sparse with footnote "Dense is ½ sparse spec shown" except FP32 and FP64. 8-GPU sparse|dense totals: FP4 144|108 PFLOPS, FP8/FP6 (one shared row — same throughput for both) 72|36 PFLOPS, FP16/BF16 36|18 PFLOPS, TF32 18|9 PFLOPS — divided by 8 for the per-GPU dense figures here (fp16TFLOPSSparse/fp8TFLOPSSparse hold the per-GPU sparse values; no sparse field exists in this schema for tf32/fp4/fp6 — their per-GPU sparse values are 2,250/18,000/9,000 TFLOPS respectively, noted here only). FP32 (600 TFLOPS/8 = 75) and FP64/FP64 Tensor Core (10 TFLOPS/8 = 1.25) are not sparsity-marked and used as-is.
int8TOPS intentionally omitted: NVIDIA's table lists the 8-GPU INT8 figure as "3 POPS" (sparse) — roughly 1/24th of the FP8 row's 72 PFLOPS, wildly inconsistent with every other generation in this collection where INT8 and FP8 throughput match closely. This looks like an error or unit typo in NVIDIA's own published table (possibly missing a digit) rather than a real architectural cut, so it's left out rather than propagated as fact — worth rechecking against a future NVIDIA source.
fp64TFLOPS (1.25 dense per GPU) is a genuine, dramatic cut from B200's 37 TFLOPS — directionally consistent with public reporting that Blackwell Ultra reallocates die area from FP64/HPC toward FP4 inference throughput, and unlike the INT8 figure this one is internally plausible (not an outlier relative to the rest of the row), so it's kept.
vramGB (288) and memoryBandwidthGBs (8000) remain corroborated across independent secondary sources rather than NVIDIA's own quick-specs page directly — that page states only an aggregate "Total GPU Memory: 2.1 TB" for the 8-GPU system (262.5GB/GPU if evenly divided), which doesn't match the widely-reported 288GB/GPU figure; likely a usable-vs-raw- capacity difference (same kind of discrepancy seen on this site's B200 entry). tdpWatts (1,400) remains a well-corroborated secondary-source figure, not a single NVIDIA-published per-GPU number. pcieGen (PCIe Gen5) is inferred from the general Blackwell-family interconnect spec (shared across B200/B300 per NVIDIA's architecture materials), not a B300-specific row in the comparison table. No transistor count or process node included — not confirmed specifically for the Ultra variant (only for baseline Blackwell/B200) and not assumed. No msrpUSD — ships through OEM/server partners.
2026-09-15 — added computeUnitCount (160 SMs), shaderCoreCount (20,480 CUDA cores) and matrixCoreCount (640 fifth-generation Tensor Cores) from NVIDIA's own "Inside NVIDIA Blackwell Ultra: The Chip Powering the AI Factory Era" developer blog post, which states "160 Streaming Multiprocessors (SMs) organized into eight Graphics Processing Clusters". 160 is the full two-die Blackwell package with nothing fused off (80 SMs per die) — which is precisely what separates Blackwell Ultra's die configuration from B200's partially-harvested 148, see this collection's B200 entry.