B200

Superseded 2026-09-01: this file previously derived per-GPU figures by dividing 8-GPU HGX B200 baseboard totals by 8. NVIDIA's official "NVIDIA Blackwell" architecture datasheet (linked from nvidia.com/en-us/data-center/hgx/ as "Read the NVIDIA Blackwell Datasheet", PDF, pulled 2026-09-01 via pdftotext) turns out to publish an "Individual Blackwell GPU Specifications" table directly — i.e. true per-GPU numbers, not something this site had to derive. All compute/ memory/TDP/interconnect fields below are read directly from that table's HGX B200 column, not derived. (NVIDIA's B200-specific product page at nvidia.com/en-us/data-center/b200/ now redirects to the general HGX platform page as of this pull — Blackwell has been superseded by Rubin in NVIDIA's current lineup.) tf32TFLOPS, bf16TFLOPS, fp16TFLOPS, fp8TFLOPS, fp6TFLOPS, fp4TFLOPS, and int8TOPS are dense figures — the datasheet states each row as sparse, with "dense is one-half of the sparse spec shown" (its own footnote 2). The published sparse figures per GPU: FP4 18 PFLOPS, FP8/FP6 9 PFLOPS (one shared row — FP6 and FP8 have identical throughput on this part), INT8 9 POPS, FP16/BF16 4.5 PFLOPS, TF32 2.2 PFLOPS — halved here for the dense fields; fp16TFLOPSSparse/fp8TFLOPSSparse/int8TOPSSparse hold the sparse figures directly (no dedicated sparse field exists in this schema for tf32/fp4/fp6, so their sparse values — 2200/18000/18000 TFLOPS respectively — are recorded here in notes only). FP32 (75 TFLOPS) and FP64/FP64 Tensor Core (37 TFLOPS, one combined row — no separate vector/matrix split published) are NOT marked with the sparsity footnote and are used as-is. memoryBandwidthGBs corrected from 7750 to 7700 to match the datasheet's precise "180 GB HBM3E | 8 TB/s" per-GPU... actually the exact line reads "180 GB HBM3E | 7.7 TB/s" for the HGX B200 column — 7700 GB/s used accordingly (the previous 7750 figure came from the old /8-derivation method and is superseded). transistorCountBillion (208) and processNode ("TSMC 4NP") describe the full dual-die Blackwell package as one GPU, per the datasheet's own architecture description ("NVIDIA Blackwell architecture GPUs pack 208 billion transistors and are manufactured using a custom-built TSMC 4NP process... two reticle-limited dies connected by a 10 TB/s chip-to-chip interconnect in a unified single GPU"). multiInstanceSupport: the datasheet's MIG row simply states "7" (spanning all three server configs in that table) rather than a per-partition VRAM size like Hopper's "@10GB each" — recorded as-is rather than computing an unstated partition size. No msrpUSD — ships through OEM/server partners. 2026-09-15 — added computeUnitCount (148 SMs), flagged here as the one figure in this file NOT traceable to an NVIDIA-published document. NVIDIA's B200 product materials omit the SM count entirely. 148 — 74 of the 80 physically present SMs enabled per die, across two dies — is reported by chipsandcheese.com's B200 architecture deep-dive, which attributes it to NVIDIA's own Hot Chips 2024 Blackwell presentation and corroborates it against hands-on testing of real B200 hardware. It is consistent with NVIDIA's Blackwell Ultra blog putting the full, nothing-fused-off two-die package at 160 SMs (see this collection's B300 entry): B200 is the partially-harvested bin of the same silicon. Caveat worth keeping for anyone re-checking this: some third-party references (e.g. Cornell CAC's GPU-architecture pages) state 160 SMs for B200, but they cite the Blackwell *Ultra* blog as the source for it — that looks like the Ultra figure applied to the wrong SKU rather than an independent measurement, so it isn't treated here as a competing source. shaderCoreCount and matrixCoreCount are deliberately left empty rather than derived as 148 x 128 and 148 x 4: the per-SM structure is right, but multiplying an already-secondhand SM count would dress a doubly-derived number up as vendor data.