Radeon Instinct MI8
AMDdatacenter| Overview | |
|---|---|
| Architecture | Fiji (GCN 3) (2017) |
| Launch date | June 2017 |
| GPU target (gfx) | gfx803 |
| Memory | |
| VRAM | 4 GB HBM |
| Memory bandwidth | 512 GB/s |
| ECC | No |
| Compute — vector | |
| FP64 | 0.512 TFLOPS |
| FP32 | 8.9 TFLOPS |
| FP16 | 8.9 TFLOPS |
| Cores & clocks | |
| Compute Units | 64 |
| Shader cores | 4,096 |
| Board & system | |
| TDP | 175 W |
| Form factor | Full-Height, Dual-Slot |
| Cooling | Passive |
| PCIe | PCIe 3.0 x16 |
Compatible ROCm versions
none — no ROCm release has ever listed gfx803 as a supported GPU target (gfx). ROCm support is granted per target, so this card is not covered by any version, including the current one. The unofficial HSA_OVERRIDE_GFX_VERSION workaround is the usual route people take — see ROCm on consumer Radeon GPUs for what it does and where it breaks.
Added 2026-09 alongside MI6 — the mid-tier card in AMD's original three-card Radeon Instinct launch lineup (with MI6 entry-level and this collection's existing MI25 as flagship, all launched June 2017). Built on Fiji (same die as the Radeon R9 Fury X/Nano), AMD's first HBM-equipped GPU architecture, hence the unusually small 4GB VRAM ceiling for a "datacenter" card — first-generation HBM's stacks topped out at 1GB each with only 4 stacks used. All figures read directly from AMD's own live "Accelerator Specifications" comparison tool (amd.com/en/products/specifications/accelerators.html), extracted from the page's embedded JSON data model, 2026-09 — the same source as MI6's entry. As with MI6, AMD's own schema defines Compute Units and Matrix Cores columns that are simply empty for this old a product, so neither figure was taken from that source; Compute Units was later derived from the published shader-core count (see below) and Matrix Cores stays empty.
fp16TFLOPSVector (8.9) is numerically identical to fp32TFLOPS (8.9) in AMD's own table — Fiji (GCN 3rd Gen) predates Rapid Packed Math (introduced with Vega/GCN 5) even further back than MI6's Polaris, so there's no 2x FP16 speedup here either, and no matrix/tensor field applies (Fiji has no Matrix Cores, introduced with CDNA/MI100 years later). eccSupport is "no" per AMD's own table — unlike MI25/MI50's HBM2 the following generation, this first-gen HBM implementation carries no ECC. targetId (gfx803) is shared with MI6 (Fiji and Polaris10 use the same gfx803 LLVM/ROCm target ISA) but doesn't cross-link to any `rocm` entry in this collection — every ROCm version tracked here already dropped gfx803 support, matching this round's MI6/K80/MI25 precedent. No MxGPU/multi-instance field, transistor count, process node, or MSRP — see MI6's entry for the same reasoning.
2026-09-15 — added computeUnitCount (64 Compute Units), derived exactly as MI6's was: GCN fixes a Compute Unit at 64 shader cores, so the 4,096 shaderCoreCount from AMD's own table gives 4,096 / 64 = 64 — the full Fiji die with nothing fused off. matrixCoreCount stays empty; Fiji has no Matrix Cores.