Radeon Instinct MI60
AMDdatacenter| Overview | |
|---|---|
| Architecture | Vega 7nm (GCN 5.1) (2018) |
| Launch date | Nov 6, 2018 (announced; AMD said shipping to datacenter customers by end of 2018) |
| Process node | 7nm FinFET |
| Transistor count | 13.2B |
| GPU target (gfx) | gfx906 |
| Memory | |
| VRAM | 32 GB HBM2 |
| Memory bandwidth | 1,000 GB/s |
| ECC | Yes |
| Compute — vector | |
| FP64 | 7.4 TFLOPS |
| FP32 | 14.8 TFLOPS |
| FP16 | 29.5 TFLOPS |
| Cores & clocks | |
| Compute Units | 64 |
| Shader cores | 4,096 |
| Board & system | |
| TDP | 300 W |
| PCIe | PCIe 4.0 x16 |
| Interconnect | Infinity Fabric Link (dual) — 200 GB/s |
| Multi-instance support | MxGPU SR-IOV (hardware virtualization, not MIG-style GPU partitioning) |
ROCm: runs, but not officially supported
AMD has never named the Radeon Instinct MI60 as a supported GPU. These ROCm releases support its gfx906 target through other cards, so it generally runs without any workaround, but AMD doesn't validate it:
Find the PyTorch build to install on this card →
Libraries on the Radeon Instinct MI60
Whether each library's own requirements cover this card. Each row links to the version and source it was checked against on library support.
| Library | Supported | Details |
|---|---|---|
| vLLM 0.30.0 | No | |
| FlashAttention-2 2.8.3.post1 | No | |
| FlashAttention-3 main (2026-09-27) | No | |
| bitsandbytes 0.50.2 | No | |
| TensorRT 11.3.0 | No | |
| llama.cpp master (2026-09-27) | Partly | needs ROCm 6.3.3 or older for the ROCm backend; otherwise Vulkan backend only |
Native low-precision formats
Whether the card's matrix hardware runs these formats natively. Without native support a format can still work, but through slower emulation or conversion, not at the card's rated speed.
| BF16 | FP8 | FP4 |
|---|---|---|
| Not documented | Not documented | Not documented |
Source: AMD ROCm 10.0.0 data types and precision support (matrix core tables); this architecture isn't in AMD's table.
Added 2026-09 — the full-die sibling of the MI50 (same Vega 20 / gfx906 silicon), and a card that comes up constantly in local-LLM discussions alongside it. Shares the MI50's ROCm history exactly, since ROCm grants support per gfx target: see the MI50 and Radeon VII entries.
Figures sourced from AMD's official launch press release of 2018-11-06 ("AMD Unveils World's First 7nm Datacenter GPUs", as distributed via GlobeNewswire): 29.5 TFLOPS FP16, 14.8 TFLOPS FP32, 7.4 TFLOPS FP64 peak theoretical, 13.2 billion transistors on a 331.46mm² die at 300W (footnote 1); 32GB HBM2 with full-chip ECC covering "HBM2 memory and internal GPU structures" (footnote 6); dual Infinity Fabric Links at "up to 200 GB/s peak theoretical GPU to GPU" per card, 264 GB/s aggregate with PCIe Gen 4 (footnote 4); MxGPU hardware virtualization. memoryBandwidthGBs (1000) follows the release's "up to 1 TB/s" wording, matching how the MI50 entry records the same memory subsystem. AMD's MI60 datasheet PDF (amd.com/system/files/documents/ radeon-instinct-mi60-datasheet.pdf) could not be retrieved at time of writing.
computeUnitCount (64) and shaderCoreCount (4096) are not stated in the press release: they are the full Vega 20 die (64 stream processors per CU; the MI50's datasheet lists 60 CUs / 3840 for the cut-down part), and are consistent with AMD's own FP32 figure — 4096 x 2 FLOP x 1.8 GHz = 14.7 TFLOPS. No INT8 figure is given in the press release, so int8TOPS is omitted rather than inferred. fp16TFLOPSVector is Vega's Rapid-Packed-Math rate on the stream processors: gfx906 predates AMD's Matrix Cores (introduced with CDNA/MI100).