Radeon Instinct MI50
AMDdatacenter| Overview | |
|---|---|
| Architecture | Vega 7nm (GCN 5.1) (2018) |
| Launch date | Nov 2018 (announced); datasheet copyright 2019, performance footnote dated Jun 19, 2019 |
| Process node | 7nm FinFET |
| GPU target (gfx) | gfx906 |
| Memory | |
| VRAM | 32 GB HBM2 |
| Memory bandwidth | 1,000 GB/s |
| ECC | Yes |
| Compute — vector | |
| FP64 | 6.6 TFLOPS |
| FP32 | 13.3 TFLOPS |
| FP16 | 26.5 TFLOPS |
| Compute — matrix / tensor | |
| INT8 | 53.6 TOPS |
| Cores & clocks | |
| Compute Units | 60 |
| Shader cores | 3,840 |
| Board & system | |
| TDP | 300 W |
| Form factor | Full-Height, Dual-Slot |
| Cooling | Passive |
| PCIe | PCIe 3.0/4.0 x16 (Gen4 capable) |
| Interconnect | Infinity Fabric Link (dual) — 184 GB/s |
| Multi-instance support | MxGPU SR-IOV (hardware virtualization, not MIG-style GPU partitioning) |
Compatible ROCm versions
Added 2026-09 — this collection's own README had specifically flagged MI50 as a candidate older Radeon Instinct card, and its gfx906 target is already referenced across roughly twenty `rocm` entries in this collection (5.0.x through 6.0.2) without a corresponding `gpus` entry until now. All figures sourced directly from AMD's official "AMD Radeon Instinct MI50 (16GB & 32GB)" datasheet (amd.com/system/files/documents/ radeon-instinct-mi50-datasheet.pdf), read via pdftotext from a mirrored copy after amd.com's own URL stopped serving the file directly (same situation as several AMD product pages elsewhere in this collection); content matches AMD's own footnote dating (Jun 19, 2019) and copyright year, so treated as a faithful copy of AMD's original.
This entry represents the 32GB variant — the datasheet states "16GB or 32GB HBM2" as a single row with identical compute/bandwidth/power specs for both capacities, so vramGB (32) is the only field that would differ; matches this site's general preference for the higher-memory SKU where one datasheet covers both (see V100 SXM2 32GB, M40 24GB). fp16TFLOPSVector (26.5) and fp32TFLOPS (13.3) are Vega 7nm's Rapid-Packed-Math throughput via standard stream processors, correctly in this schema's vector field — Vega still predates AMD's dedicated Matrix Cores (introduced with CDNA/MI100 the following generation). int8TOPS (53.6) is likewise a CU-based packed-math rate, not Matrix-Core throughput, but is placed in this schema's matrix/tensor-throughput field since no vector-INT8 field exists — noted here for anyone comparing it against later CDNA entries' genuinely Matrix-Core-derived INT8 figures. eccSupport is "Yes" and, per the datasheet's own "ECC (Full-chip): Yes" row, full-chip (HBM2 plus internal GPU structures) — an upgrade over MI25's HBM2-only ECC the prior generation.
interconnectBandwidthGBs (184) is the dual Infinity-Fabric-Link GPU-to-GPU bandwidth specifically (AMD's footnote: "184 GB/s peak theoretical GPU to GPU ... per GPU card"), distinct from pcieGen's host link; AMD's footnote separately states these combine to a 248 GB/s aggregate I/O figure when both are counted together, not modeled as a separate field here. No transistor count or MSRP — AMD doesn't publish Instinct list prices (see this collection's MI100/MI25 entries).